Common VAX Instructions

Arithmetic and Move Instructions

ADDxx ADWC
SUBxx SBWC
MULxx EMUL
DIVxx EDIV
INCx DECx
MOVx MOVAx MOVZxx MNEGx CLRx
CVTxx

Compare and Branch Instructions

CMPx TSTx
Bxxxx JMP
BSBx JSB RSB CALLG CALLS RET
AOBLxx SOBGxx

Bit Pushing Instructions

ASHx ROTL
BICxx BISxx BITx XORxx
MCOMx

Character String Instructions

MOVCx
CMPCx
ASHP

Miscellaneous Instructions

HALT NOP
PUSHR POPR PUSHL PUSHAx


ADDxx

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Purpose: Perform arithmetic addition

Format:

opcode add.rx,sum.mx ;2 operand
opcode add1.rx,add2.rx,sum.wx ;3 operand

Operation:

sum = sum + add ;2 operand
sum = add1 + add2 ;3 operand

C. Codes:

N = {sum LSS 0}, Z = {sum EQL 0}, V = {overflow}, C = 0 (floating), C = {carry from MSB} (integer)

Opcodes:

80 ADDB2 Add byte 2 operand
81 ADDB3 Add byte 3 operand
A0 ADDW2 Add word 2 operand
A1 ADDW3 Add word 3 operand
C0 ADDL2 Add long 2 operand
C1 ADDL3 Add long 3 operand
40 ADDF2 Add F_floating 2 operand
41 ADDF3 Add F_floating 3 operand
60 ADDD2 Add D_floating 2 operand
61 ADDD3 Add D_floating 3 operand
40FD ADDG2 Add G_floating 2 operand
41FD ADDG3 Add G_floating 3 operand
60FD ADDH2 Add H_floating 2 operand
61FD ADDH3 Add H_floating 3 operand


ADWC

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Purpose: Add with carry - perform extended-precision addition

Format:

opcode add.rl,sum.ml

Operation:

sum = sum + add + C

C. Codes

N = {sum LSS 0}, Z = {sum EQL 0}, V = {integer overflow}, C = {carry from MSB}

Opcode:

D8 ADWC Add with carry


AOBLxx

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Purpose: Add one and branch - increment integer loop count and loop

Format:

opcode limit.rl,index.ml,displ.bb

Operation:

index = index + 1; if {{AOBLSS} and {index LSS limit}} or {{AOBLEQ} and {index LEQ limit}} then PC = PC + SEXT (displ)

C. Codes:

N = {index LSS 0}, Z = {index EQL 0}, V = {integer overflow}, C = C

Opcodes:

F2 AOBLSS Add one, branch less than
F3 AOBLEQ Add one, branch less or equal


ASHx

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Purpose: Shift of integer

Format:

opcode cnt.rb,src.rx,dst.wx

Operation:

dst = src shifted cnt bits

C. Codes:

N = {dst LSS 0}, Z = {dst EQL 0}, V = {integer overflow}, C = 0

Opcodes:

78 ASHL Arithmetic shift long
79 ASHQ Arithmetic shift quad

Description:

src is arithmetically shifted by the number of bits specified by cnt and the result is placed in dst. Positive cnt shifts left bringing 0's into the LSB. Negative cnt shifts right bringing copies of the MSB into the MSB. Zero cnt copies dst to src unaffected.


ASHP

Purpose: Arithmetic shift and round packed - scale numeric content of a packed decimal string by a power of ten

Format:

opcode cnt.rb,srclen.rw,srcaddr.ab,round.rb, dstlen.rw,dstaddr.ab

Operation:

{dst string} = {{src string} + {round <3:0>*(10**(-cnt-1))}} * (10**cnt);

C. Codes

N = {{dst string} LSS 0}, Z = {{dst string} EQL 0}, V = {decimal overflow}, C = 0

Opcodes:

F8 ASHP Arithmetic shift packed

Description:

src as specified by srclen and srcaddr is scaled by a power of 10 specified by cnt. dst is replaced by the result. A positive cnt effectively multiplies, a negative cnt effectively divides and a zero cnt just moves src to dst while affecting the condition codes. If cnt is negative the result is rounded using round. After execution:

R0 = 0

R1 = address of the byte containing the most-significant digit of the source string

R2 = 0

R3 = address of the byte containing the most-significant digit of the destination string


Bxxxx

Purpose: Branch - test condition code(s)

Format:

opcode displ.bb

Operation:

if {condition} then PC = {PC + SEXT (displ)}

C. Codes:

Not affected

Opcodes:

12 {Z EQL 0} BNEQ Branch not equal (s) BNEQU Branch not equal (u)
13 {Z EQL 1} BEQL Branch equal (s) BEQLU Branch equal (u)
14 {(N OR Z) EQL 0} BGTR Branch greater than (s)
15 {(N OR Z) EQL 1} BLEQ Branch less or equal (s)
18 {N EQL 0} BGEQ Branch greater, equal (s)
19 {N EQL 1} BLSS Branch less than (s)
1A {(C OR Z) EQL 0} BGTRU Branch greater than (u)
1B {(C OR Z) EQL 1} BLEQU Branch less or equal (u)
1C {V EQL 0} BVC Branch overflow clear
1D {V EQL 1} BVS Branch overflow set
1E {C EQL 0} BGEQU Branch greater, equal (u) BCC Branch carry clear
1F {C EQL 1} BLSSU Branch less than (u) BCS Branch carry set

legend: s - signed, u - unsigned

Description:

The condition codes are tested and if the condition indicated by the instruction is met, the sign extended branch displacement is added to the PC.


BICxx

Purpose: Bit clear - perform complemented AND of two integers

Format:

opcode mask.rx,dst.mx ;2 operand
opcode mask.rx,src.rx,dst.rx ;3 operand

Operation:

dst = dst AND {NOT mask} ;2 operand
dst = src AND {NOT mask} ;3 operand

C. Codes:

N = {dst LSS 0}, Z = {dst EQL 0}, V = 0, C = C

Opcodes:

8A BICB2 Bit clear byte, 2 operand
8B BICB3 Bit clear byte, 3 operand
AA BICW2 Bit clear word, 2 operand
AB BICW3 Bit clear word, 3 operand
CA BICL2 Bit clear long, 2 operand
CB BICL3 Bit clear long, 3 operand

Description:

In 2 operand format, dst is ANDed with the ones complement of mask and dst is replaced by the result. In 3 operand format, src is ANDed with the ones complement of mask and dst is replaced by the result.


BISxx

Purpose: Bit set - perform logical inclusive OR of two integers

Format:

opcode mask.rx,dst.mx ;2 operand
opcode mask.rx,src.rx,dst.rx ;3 operand

Operation:

dst = dst OR mask ;2 operand
dst = src OR mask ;3 operand

C. Codes:

N = {dst LSS 0}, Z = {dst EQL 0}, V = 0, C = C

Opcodes:

88 BISB2 Bit set byte, 2 operand
89 BISB3 Bit set byte, 3 operand
A8 BISW2 Bit set word, 2 operand
A9 BISW3 Bit set word, 3 operand
C8 BISL2 Bit set long, 2 operand
C9 BISL3 Bit set long, 3 operand

Description:

In 2 operand format, dst is ORed with mask and dst is replaced by the result. In 3 operand format, src is ORed with mask and dst is replaced by the result.


BITx

Purpose: Test a set of bits for all zero

Format:

opcode mask.rx,src.rx

Operation:

tmp = {src AND mask}

C. Codes:

N = {tmp LSS 0}, Z = {tmp EQL 0}, V = 0, C = C

Opcodes:

93 BITB Bit test byte
B3 BITW Bit test word
D3 BITL Bit test long

Description:

mask is ANDed with src. Both operands are unaffected. The only action is to affect the condition codes.

BSBx

Purpose: Branch to subroutine - transfer control to subroutine

Format:

opcode displ.bx

Operation:

-(SP) = PC; PC = {PC + SEXT (displ)}

C. Codes:

Not affected

Opcodes:

10 BSBB Branch to sub., byte displ.
30 BSBW Branch to sub., word displ.

Description:

PC is pushed onto the stack as a longword and the branch is taken.


CALLG

Purpose: Call with general argument list - invoke a procedure with actual arguments from anywhere in memory

Format:

opcode arglist.ab,dst.ab

Operation:

{align stack}; {create stack frame}; {set arithmetic trap enables}; {set new values of AP, FP, PC}

C. Codes:

N = 0, Z = 0, V = 0, C = 0

Opcode:

FA CALLG Call proc., general arglist

Description:

SP is saved in a temporary (tmp) and then bits 1:0 of SP are cleared so the stack is longword aligned. The procedure entry mask (pointed to by dst) is scanned from bit 11 to bit 0 and the contents of the registers whose numbers correspond to set bits in the mask are pushed on the stack as longwords. Next AP, FP and the current PC are pushed onto the stack as longwords. The condition codes are cleared. A longword containing the saved two low bits of SP in bits 31:30 (tmp), 0 in bits 29:28, the low 12 bits of the entry mask in bits 27:16 and the PSW in bits 15:0 with T cleared is pushed on the stack. A longword 0 is pushed on the stack (for the condition handler). FP is replaced by SP, AP is replaced by arglist. The trap enables in PSW are set to a known state. Integer and decimal overflow are set according to bits 14 and 15 of the entry mask respectively. The floating underflow bit is cleared and the T-bit is unaffected. PC is replaced by dst + 2, skipping the entry mask and transferring control to the byte beyond the mask.


CALLS

Purpose: Call with stack argument list - invoke a procedure with actual arguments on the stack

Format:

opcode numarg.rl,dst.ab

Operation:

{push arg count}; {align stack}; {create stack frame}; {set arithmetic trap enables}; {set new values of AP, FP, PC}

C. Codes:

N = 0, Z = 0, V = 0, C = 0

Opcode:

FB CALLS Call proc. with stack arglist

Description:

numarg is pushed on the stack as a longword (byte 0 contains the number of arguments, the high-order 24 bits are used by Digital software), SP is saved in a temporary (tmp) and then bits 1:0 of SP are cleared so the stack is longword aligned. The procedure entry mask (pointed to by dst) is scanned from bit 11 to bit 0 and the contents of the registers whose numbers correspond to set bits in the mask are pushed on the stack as longwords. AP, FP and the current PC are pushed onto the stack as longwords. The condition codes are cleared. A longword containing the saved two low bits of SP in bits 31:30 (tmp), 1 in bit 29, a 0 in bit 28, the low 1 bits of the entry mask in bits 27:16 and the PSW in bits 15:0 with T cleared is pushed on the stack. A longword 0 is pushed on the stack (for the condition handler address within the procedure). FP is replaced by SP, AP is set to the saved SP (value of SP after numarg was pushed. The trap enables in PSW are set to a known state. Integer and decimal overflow are set according to bits 14 and 15 of the entry mask respectively. The floating underflow bit is cleared and the T-bit is unaffected. PC is replaced by dst + 2, skipping the entry mask and transferring control to the byte beyond the mask.


CLRx

Purpose: Clear or zero a scalar quantity

Format:

opcode dst.wx

Operation:

dst = 0

C. Codes:

N = 0, Z = 1, V = 0, C = 0

Opcodes:

94 CLRB Clear byte
B4 CLRW Clear word
D4 CLRL Clear long
7C CLRQ Clear quad
7CFD CLRO Clear octa
D4 CLRF Clear F_floating
7C CLRD Clear D_floating
7C CLRG Clear G_floating
7CFD CLRH Clear H_floating

Description:

The destination operand is replaced by 0.


CMPx

Purpose: Arithmetic comparison between two scalar quantities

Format:

opcode scr1.rx,src2.rx

Operation:

src1 - src2

C. Codes:

N = {src1 LSS src2}, Z = {src1 EQL src2}, V = 0, C = {src1 LSSU src2} (integer), C = 0 (floating)

Opcodes:

91 CMPB Compare byte
B1 CMPW Compare word
D1 CMPL Compare long
51 CMPF Compare F_floating
71 CMPD Compare D_floating
51FD CMPG Compare G_floating
71FD CMPH Compare H_floating

Description:

src1 is compared with src2. The only action is to affect the condition codes.


CMPCx

Purpose: Compare two character strings

Format:

opcode len.rw,src1addr.ab,src2addr.ab ;3 operand
opcode src1len.rw,src1addr.ab,fill.rb src2len.rw,src2addr.ab;5 operand

Operation:

{compare two strings with optional filling}

C. Codes:

[final codes reflect last affecting of codes in the operation.] N = {{first byte} LSS {second byte}}, Z ={{first byte} EQL {second byte}}, V = 0, C = {{first byte} LSSU {second byte}}

Opcodes:

29 CMPC3 Compare character 3 operand
2D CMPC5 Compare character 5 operand

Description:

In 3-operand format the bytes of string 1 specified by len and src1addr are compared with string 2 specified by len and src2addr. In 5-operand format the bytes of string 1 specified by src1len and src1addr are compared with string 2 specified by src2len and src2addr. If one string is longer than the other the shorter string is conceptually extended by appending bytes with the value of fill to the end. Comparison proceeds until all the bytes have been examined or inequality is detected. Condition codes are affected by the last character comparison.

After execution of CMPC3:

R0 = number of bytes remaining in string 1 (including byte that terminated comparison); R0 is 0 only is strings are equal

R1 = address of the byte in string 1 that terminated comparison; if strings are equal, address of one byte beyond string 1

R2 = R0

R3 = address of the byte in string 2 that terminated comparison; if strings are equal, address of one byte beyond string 2

After execution of CMPC5:

R0 = number of bytes remaining in string 1 (including byte that terminated comparison); R0 is 0 only if string1 and string 2 are of equal length or string 1 was exhausted before comparison terminated

R1 = address of the byte in string 1 that terminated comparison; if comparison did not terminate before string 1 exhausted, address of one byte beyond string 1

R2 = number of bytes remaining in string 2 (including byte that terminated comparison); R2 is 0 only if string 1 and string 2 are of equal length or string 2 was exhausted before comparison terminated

R3 = address of the byte in string 2 that terminated comparison; if conmparison did not terminate before string 2 was exhausted, address of one byte beyond string 2


CVTxx

Purpose: Convert a signed quantity to a different signed data type

Format:

opcode src.rx,dst.wy

Operation:

dst = conversion or src

C. Codes:

N = dst LSS 0, Z = dst EQL 0, C = 0 V = {src cannot be represented in dst}

Opcodes: See table below:

from/to |Byte  |Word  |Long  |F_floa|D_floa|G_float|H_float| 

--------|------|------|------|------|------|-------|-------| 

Byte    |      |99   x|98   x|4C   e|6C   e|4CFD  e|6CFD  e| 

Word    |33   t|      |32   x|4D   e|6D   e|4DFD  e|6DFD  e| 

Long    |F6   t|F7   t|      |4E   r|6E   e|4EFD  e|6EFD  e| 

F_float |48   t|49   t|4A   t|      |56   e|99FD  e|98FD  e| 

D_float |68   t|69   t|6A   t|76   r|      |       |32FD  e| 

G_float |48FD t|49FD t|4AFD t|33FD r|      |       |56FD  e| 

H_float |68FD t|69FD t|6AFD t|F6FD r|F7FD r|76FD  r|       | 

--------|------|------|------|------|------|-------|-------| 

legend: t - truncate, x - sign extend, e - exact, r - rounded, 

4B CVTRFL Convert and round F_floating to long
6B CVTRDL Convert and round D_floating to long
4BFD CVTRGL Convert and round G_floating to long
6BFD CVTRHL Convert and round H_floating to long


DECx

Purpose: Decrement - subtract 1 from an integer

Format:

opcode dif.mx

Operation:

dif = dif - 1

C. Codes:

N = dif LSS 0, Z = dif EQL 0 V = {integer overflow}, C = {borrow from MSB}

Opcodes:

97 DECB Decrement byte
B7 DECW Decrement word
D7 DECL Decrement long

Description:

One is subtracted from the dif operand and the dif operand is replaced by the result.


DIVxx

Purpose: Perform arithmetic division

Format:

opcode divr.rx,quo.mx ;2 operand
opcode divr.rx,divd.rx,quo.wx ;3 operand

Operation:

quo = quo / divr ;2 operand
quo = divd / divr ;3 operand

C. Codes:

N = {quo LSS 0}, Z = {quo EQL 0}, C = 0, V = {overflow or {divr EQL 0}}

Opcodes:

86 DIVB2 Divide byte 2 operand
87 DIVB3 Divide byte 3 operand
A6 DIVW2 Divide word 2 operand
A7 DIVW3 Divide word 3 operand
C6 DIVL2 Divide long 2 operand
C7 DIVL3 Divide long 3 operand
46 DIVF2 Divide F_floating 2 operand
47 DIVF3 Divide F_floating 3 operand
66 DIVD2 Divide D_floating 2 operand
67 DIVD3 Divide D_floating 3 operand
46FD DIVG2 Divide G_floating 2 operand
47FD DIVG3 Divide G_floating 3 operand
66FD DIVH2 Divide H_floating 2 operand
67FD DIVH3 Divide H_floating 3 operand


EDIV

Purpose: Perform extended-precision division

Format:

opcode divr.rl,divd.rq,quo.wl,rem.wl

Operation:

quo = divd/divr; rem = REM (divd, divr)

C. Codes:

N = {quo LSS 0}, Z = {quo EQL 0}, C = 0, V = {{integer overflow} OR {divr EQL 0}}

Opcode:

7B EDIV Extended divide


EMUL

Purpose: Perform extended-precision multiplication

Format:

opcode mulr.rl,muld.rl,add.rl,prod.wq

Operation:

prod = {{muld * mulr} + SEXT (add)}

C. Codes:

N = {prod LSS 0}, Z = {prod EQL 0}, V = 0, C = 0

Opcode:

7A EMUL Extended multiply

Description:

mulr is multiplied by muld to give a double length is then stored in prod.


HALT

Purpose: Stop processor operation

Format:

opcode

Operation:

If PSL<current_mode> NEQU kernel then {reserved to Digital opcode fault} else {halt the processor}

C. Codes:

N = 0, Z = 0, V = 0, C = 0 (fault) Unaffected (processor halt)

Opcode:

00 HALT Halt

Description:

If process is running in kernel mode, the processor is halted. Otherwise, an opcode reserved to Digital fault occurs. This opcode is 0 to trap many branches to data.


INCx

Purpose: Increment - add 1 to an integer

Format:

opcode sum.mx

Operation:

sum = sum + 1

C. Codes:

N = {sum LSS 0}, Z = {sum EQL 0}, V = {integer overflow}, C = {carry from MSB}

Opcodes:

96 INCB Increment byte
B6 INCW Increment word
D6 INCL Increment long

Description:

One is added to the sum operand and the sum operand is replaced by the result.


JMP

Purpose: Transfer control

Format:

opcode dst.ab

Operation:

PC = dst

C. Codes:

Not affected

Opcode:

17 JMP Jump


JSB

Purpose: Jump to subroutine - transfer control to subroutine

Format:

opcode dst.ab

Operation:

-(SP) = PC; PC = dst

C. Codes:

Not affected

Opcode:

16 JSB Jump to subroutine

Description:

PC is pushed onto the stack as a longword and the jump is taken.


MCOMx

Purpose: Move the logical complement of an integer

Format:

opcode src.rx,dst.wx

Operation:

dst = NOT src

C. Codes:

N = {dst LSS 0}, Z = {dst EQL 0}, V = 0, C = C

Opcodes:

92 MCOMB Move complemented byte
B2 MCOMW Move complemented word
D2 MCOML Move complemented long

Description:

The destination operand is replaced by the ones complement of the source operand.


MNEGx

Purpose: Move the arithmetic negation of a scalar quantity

Format:

opcode src.rx,dst.wx

Operation:

dst = -scr

C. Codes:

N = {dst LSS 0}, Z = {dst EQL 0}, V = 0 (floating), V = overflow (integer), C = {dst NEQ 0} (integer), C = 0 (floating)

Opcodes:

8E MNEGB Move negated byte
AE MNEGW Move negated word
CE MNEGL Move negated long
52 MNEGF Move negated F_floating
72 MNEGD Move negated D_floating
52FD MNEGG Move negated G_floating
72FD MNEGH Move negated H_floating

Description:

The destination operand is replaced by the negative of the source operand.


MOVx

Purpose: Move a scalar quantity

Format:

opcode src.rx,dst.wx

Operation:

dst = src

C. Codes:

N = {dst LSS 0}, Z = {dst EQL 0}, V = 0, C = C

Opcodes:

90 MOVB Move byte
B0 MOVW Move word
D0 MOVL Move long
7D MOVQ Move quad
7DFD MOVO Move octa
50 MOVF Move F_floating
70 MOVD Move D_floating
50FD MOVG Move G_floating
70FD MOVH Move H_floating

Description:

The destination operand is replaced by the source operand. The source operand is not affected.


MOVAx

Purpose: Move address - calculate address of quantity

Format:

opcode src.ax,dst.wl

Operation:

dst = src

C. Codes:

N = {dst LSS 0}, Z = {dst EQL 0}, V = 0, C = 0

Opcodes:

9E MOVAB Move address of byte
3E MOVAW Move address of word
7E MOVAQ Move address of quad
7EFD MOVAO Move address of octa
DE MOVAF Move address of F_floating
7E MOVAD Move address of D_floating
7E MOVAG Move address of G_floating
7EFD MOVAH Move address of H_floating

Description:

dst is replaced by the address of src. The context in which src is evaluated is given by the data type of the instruction. The operand at the address of src is not referenced.


MOVCx

Purpose: Move character string or block of memory

Format:

opcode len.rw,srcaddr.ab,dstaddr.ab ;3 operand
opcode srclen.rw,srcaddr.ab,fill.rb, dstlen.rw,dstaddr.ab;5 operand

Operation:

{dst string} = {src string}

Opcodes:

28 MOVC3 Move character 3 operand
2C MOVC5 Move character 5 operand

Description:

dst as specified by dstaddr and len (3 operand) or dstlen (5 operand) is replaced by src as specified by srcaddr and len (3 operand) or srclen (5 operand). If dst is longer than src (5 operand only), the highest addresses of dst that are not filled by src are instead filled with fill. If dst is shorter than src, the copied string is truncated to fit in src. The operation of the instruction is such that any overlap of src and dst will not affect the result.

After execution of MOVC3:

R0 = 0

R1 = address of one byte beyond the source string

R2 = 0

R3 = address of one byte beyond the destination string

R4 = 0

R5 = 0

After execution of MOVC5:

R0 = number of unmoved bytes remaining in the source string. R0 is nonzero only if source string is longer than the destination string

R1 = address of one byte beyond the last byte in source string that was moved

R2 = 0

R3 = address of one byte beyond the destination string

R4 = 0

R5 = 0


MOVZxx

Purpose: Convert an unsigned integer to a wider unsigned integer (move zeroed)

Format:

opcode src.rx,dst.wy

Operation:

dst = ZEXT (src)

C. Codes:

N = 0, Z = {dst EQL 0}, V = 0, C = C

Opcodes:

9B MOVZBW Move zero-extended byte to word
9A MOVZBL Move zero-extended byte to long
3C MOVZWL Move zero-extended word to long

Description:

For MOVZBW, bits 7:0 of dst are replaced by src, bits 15:8 are zeroed. For MOVZBL, bits 7:0 of dst are replaced by src, bits 31:8 are zeroed. For MOVZWL, bits 15:0 of dst are replaced by src, bits 31:16 are zeroed.


MULxx

Purpose: Perform arithmetic multiplication

Format:

opcode mulr.rx,prod.mx ;2 operand
opcode mulr.rx,muld.rx,prod.wx ;3 operand

Operation:

prod = prod * mulr ;2 operand
prod = muld * mulr ;3 operand

C. Codes:

N = {prod LSS 0}, Z = {prod EQL 0}, V = {overflow}, C = 0

Opcodes:

84 MULB2 Multiply byte 2 operand
85 MULB3 Multiply byte 3 operand
A4 MULW2 Multiply word 2 operand
A5 MULW3 Multiply word 3 operand
C4 MULL2 Multiply long 2 operand
C5 MULL3 Multiply long 3 operand
44 MULF2 Multiply F_floating 2 operand
45 MULF3 Multiply F_floating 3 operand
64 MULD2 Multiply D_floating 2 operand
65 MULD3 Multiply D_floating 3 operand
44FD MULG2 Multiply G_floating 2 operand
45FD MULG3 Multiply G_floating 3 operand
64FD MULH2 Multiply H_floating 2 operand
65FD MULH3 Multiply H_floating 3 operand


NOP

Purpose: No operation is performed

Format:

opcode

C. Codes:

Not affected

Opcode:

01 NOP No Operation


POPR

Purpose: Restore multiple registers from stack

Format:

opcode mask.rw

Operation:

Restore registers in order R14 .. R0

C. Codes:

Not affected

Opcode:

BA POPR Pop registers

Description:

The contents of the registers whose number corresponds to set bits in the mask operand are replaced by longwords popped from the stack. R[n] is pushed if mask <n> is set. The mask is scanned from bit 14 to bit 0. Bit 15 is ignored.


PUSHAx

Purpose: Push address - calculate address of quantity

Format:

opcode src.ax

Operation:

-(SP) = src

C. Codes:

N = {result LSS 0}, Z = {result EQL 0}, V = 0, C = 0

Opcodes:

9F PUSHAB Push address of byte
3F PUSHAW Push address of word
DF PUSHAL Push address of long
7F PUSHAQ Push address of quad
7FFD PUSHAO Push address of octa
DF PUSHAF Push address of F_floating
7F PUSHAD Push address of D_floating
7F PUSHAG Push address of G_floating
7FFD PUSHAH Push address of H_floating

Description:

The address of src is pushed on the stack. The context in which src is evaluated is given by the data type of the instruction. The operand at the address of src is not referenced. PUSHAx is equivalent to MOVAx src,-(SP) but is shorter.


PUSHL

Purpose: Push source operand onto stack

Format:

opcode src.rl

Operation:

-(SP) = src

C. Codes:

N = {src LSS 0}, Z = {src EQL 0}, V = 0, C = C

Opcode:

DD PUSHL Push long

Description:

The long word source operand is pushed on the stack.


PUSHR

Purpose: Save multiple registers on stack

Format:

opcode mask.rw

Operation:

Save registers in order R0 .. R14

C. Codes:

Not affected

Opcode:

BB PUSHR Push registers

Description:

The contents of the registers whose number corresponds to set bits in the mask operand are pushed on the stack as longwords. R[n] is pushed if mask <n> is set. The mask is scanned from bit 14 to bit 0. Bit 15 is ignored.


RET

Purpose: Return from called procedure

Format:

opcode

Operation:

{restore SP from FP}; {restore registers}; {drop stack alignment}; {if CALLS, remove arglist}; {restore PSW}

C. Codes:

N = tmp1<3>, Z = tmp1<2>, V = tmp1<1>, C = tmp1<0>

Opcode:

04 RET Return from procedure

Description:

SP is replaced with FP plus 4. A longword containing stack alignment in bits 31:30, a CALLS/CALLG flag in bit 29, the low 12 bits of the procedure entry mask in bits 27:16 and a saved PSW in bits 15:0 is popped from the stack and saved in a temporary (tmp1). PC, FP and AP are replaced by longwords popped from the stack. A register restore mask is formed from bits 27:16 of tmp1. Scanning from bit 0 to bit 11 of tmp1, the contents of the registers whose numbers indicated by set bits in the restore mask are replaced by longwords popped from the stack. SP is incremented by bits 31:30 of tmp1. PSW is replaced by bits 15:0 of tmp1. If bit 29 of tmp1 is 1 indicating a CALLS was used) a longword containing the number of arguments is popped from the stack. Four times the unsigned value of the low byte of this longword is added to SP and SP is replaced by the result.


ROTL

Purpose: Rotate of integer

Format:

opcode cnt.rb,src.rl,dst.wl

Operation:

dst = src rotated cnt bits

C. Codes:

N = {dst LSS 0}, Z = {dst EQL 0}, V = 0, C = C

Opcode:

9C ROTL Rotate long

Description:

The source operand is rotated logically by the number of bits specified by the count operand and the destination is replaced by the result. The source operand is unaffected. A positive count rotates to the left, a negative to the right. A 0 count leaves the value unaffected.


RSB

Purpose: Return from subroutine return control from subroutine

Format:

opcode

Operation:

PC = (SP)+

C. Codes:

Not affected

Opcode:

05 RSB Return from subroutine


SOBGxx

Purpose: Subtract one and branch - decrement integer loop count and loop

Format:

opcode index.ml,displ.bb

Operation:

index = index - 1; if {{SOBGEQ} and {index GEQ 0}} or {{SOBGTR} and {index GTR 0}} then PC = PC + SEXT (displ)

C. Codes:

N = {index LSS 0}, Z = {index EQL 0}, V = {integer overflow}, C = C

Opcodes:

F4 SOBGEQ Subtract one, branch greater or equal
F5 SOBGTR Subtract one, branch greater than


SUBxx

Purpose: Perform arithmetic subtraction

Format:

opcode sub.rx,dif.mx ;2 operand
opcode sub.rx,min.rx,dif.wx ;3 operand

Operation:

dif = dif - sub ;2 operand
dif = min - sub ;3 operand

C. Codes:

N = {dif LSS 0}, Z = {dif EQL 0}, V = {overflow}, C = 0 (floating), C = {borrow from MSB (integer)}

Opcodes:

82 SUBB2 Subtract byte 2 operand
83 SUBB3 Subtract byte 3 operand
A2 SUBW2 Subtract word 2 operand
A3 SUBW3 Subtract word 3 operand
C2 SUBL2 Subtract long 2 operand
C3 SUBL3 Subtract long 3 operand
42 SUBF2 Subtract F_floating 2 operand
43 SUBF3 Subtract F_floating 3 operand
62 SUBD2 Subtract D_floating 2 operand
63 SUBD3 Subtract D_floating 3 operand
42FD SUBG2 Subtract G_floating 2 operand
43FD SUBG3 Subtract G_floating 3 operand
62FD SUBH2 Subtract H_floating 2 operand
63FD SUBH3 Subtract H_floating 3 operand


SBWC

Purpose: Subtract with carry - perform extended-precision subtraction

Format:

opcode sub.rl,dif.ml

Operation:

dif = dif - sub - C

C. Codes

N = {dif LSS 0}, Z = {dif EQL 0}, V = {integer overflow}, C = {carry into MSB}

Opcode:

D9 SBWC Subtract with carry


TSTx

Purpose: Arithmetic compare of a scalar to 0.

Format:

opcode src.rx

Operation:

src - 0

C. Codes:

N = {src LSS 0}, Z = {src EQL 0}, V = 0, C = 0

Opcodes:

95 TSTB Test byte
B5 TSTW Test word
D5 TSTL Test long
53 TSTF Test F_floating
73 TSTD Test D_floating
53FD TSTG Test G_floating
73FD TSTH Test H_floating

Description:

The condition codes are affected according to the values of src.


XORxx

Purpose: Perform logical exclusive OR of two integers

Format:

opcode mask.rx,dst.mx ;2 operand
opcode mask.rx,src.rx,dst.rx ;3 operand

Operation:

dst = dst XOR mask ;2 operand
dst = src XOR mask ;3 operand

C. Codes:

N = {dst LSS 0}, Z = {dst EQL 0}, V = 0, C = C

Opcodes:

88 XORB2 Exclusive OR byte, 2 operand
89 XORB3 Exclusive OR byte, 3 operand
A8 XORW2 Exclusive OR word, 2 operand
A9 XORW3 Exclusive OR word, 3 operand
C8 XORL2 Exclusive OR long, 2 operand
C9 XORL3 Exclusive OR long, 3 operand

Description:

In 2 operand format, dst is XORed with mask and dst is replaced by the result. In 3 operand format, src is XORed with mask and dst is replaced by the result.