Register Transfer Language (RTL)

last updated 10/04/01

RTL 

RTL is a simple, human-oriented language to specify the operations, register communication and timing of the steps that take place within a CPU to carry out higher level (user programmable) instructions.  

A step is the unit of operation done in one clock cycle.

Parallel and Serial operations are possible at this level.  Some operations can be done in other parts of the CPU simultaneously--they are independent of each other.  Other operations must follow in sequence because of dependencies.

Parallel Operations: Place the operations on the same line and separate with semicolons.  These operations are done in the same clock cycle.

operation1; operation2;...

Serial: Just sequence the operations on subsequent lines. Each operation takes a clock cycle.

op1
op2

 

 


RTL Operations

Operation Category Syntactic notation
Transfer of data between registers RegA -> RegB [,RegC]...
Reg field -> RegB [,RegC]...

multiple target registers are loaded in parallel

Load a register with certain, common constants (e.g., 0, 1, 2, 4). Only certain registers may have this operation. Typically X and Y. All registers may have a 0->Rn operation, however. 4 -> X
Memory operations.  Implicitly use MAR and MDR Read
Write
Wait --
clock cycles are wasted until the operation is complete
ALU operations.  These operations only apply to X and Y registers and place the result in Z Add
Sub
etc.
There may be some simple IF-THEN [-ELSE] control.  The conditions are based on status flags only or zero contents.

 

 


Memory Access

Reading a location Writing a value to a location
RegX -> MAR
"Read"
"Wait"
MDR -> RegY
RegX -> MAR
RegY -> MDR
"Write"
"Wait"
The "wait" operation can be initiated with the "read" or "write".

Other non-memory operations may be performed between Write/Read and Wait

Example MOVL R4, -(SP)

R4 -> MDR
SP->X, 4-> Y
Add
Z -> SP, MAR
Write, Wait

 


Typical ALU Operation

Example ADDL (R5), R0

R0 -> X
R5 -> MAR
read, wait
MDR -> Y
Add
Z -> R0

 

 

 

 


Instruction Cycle Implementation

Fetch instruction PC -> MAR
Read
Wait
MDR -> IR
Update PC PC -> X
4 -> Y
Add
Z -> PC
Parallel Fetch and PC Update PC -> MAR, X
Read, 4->Y
Add
Z-> PC, Wait
MDR -> IR
Decode instruction and Fetch operand
/* We're assuming either register direct or register deferred modes */
IF source is register THEN
R(IRreg) -> X
ELSE
R(IRreg) -> MAR
Read
Wait
MDR -> X
ENDIF
Execute and Store Results Add /*assume this is the operation*/
IF RAMfield is register THEN
Z -> R(IRram)
ELSE
Z-> MDR
(IRram)-> MAR
Write
Wait

 


Examples of RTL coding

ADDL R0,R1
DECL R3
ADDL R5,@R6
ADDL (R3)+,R1
MOVL R5,-(SP)
MOVL 8(R0),R0 
MOVAL 8(R0),R1
ADDL @4(R3),@0(R3)

 

 

 

 


Flow Control

Jumps can be implemented in two ways. The target address of the jump could be encoded fully into the instruction itself, or the distance to the target could be encoded.

Label of target is coded as absolute address fetch instruction...
IRram->PC
The label of target is an offset relative to the jump instruction itself--
the PC is used as a reference point
fetch instruction...
IRram-> X
PC -> Y
Add
Z -> PC

We must account for where PC is pointing at time of addition. What value is currently in the PC at the time of the execution of the instruction?

 

 

 


Conditional jumps

Remember that each instruction is self contained regarding execution. No recorded memory is kept about the previous instructions, except in the condition codes.

Z flag: 1=zero; 0=non-zero

N flag: 1=negative; 0=non-negative

Z N Combination Meaning

Z N Meaning
1 0 equal to
0 1 less than
0 0 greater than
1 1 impossible

Relational Operators and ZN pairs

ZN pairs Meaning
10 =
01 <
00 >
01 | 10 <=
*0 >= (ignore Z)
0* <> (ignore N)
*1 < (since 11 is impossible)
 
 

Conditional Jumps Implementation

fetch instruction...
IF coded cond matches CC THEN
IRram-> X
PC -> Y
Add
Z -> PC

 

 

 

 


Subroutine calls

fetch instruction...
SP->X; 4->Y
Sub
Z->MAR,SP
PC->MDR; PC->X
Write; IRdst->Y
Add
Wait; Z->PC

Return instruction as exercise

 

 

 


Von Neumann Bottleneck

Speed enhancements